1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, relates to an improved method of manufacturing a semiconductor device to form a gate.
2. Description of the Related Art
With the rapid development of the semiconductor industry, critical dimensions of semiconductors have been continuously shrunk. Requirements for gate height and topography control has become stricter. During the fabrication process of a semiconductor device, chemical mechanical planarization (CMP) processing needs to be performed on the device several times. Currently, as part of the latest fabrication process, high dielectric constant metal gate (i.e. high-K metal gate) gradually becomes a main stream. Generally, the high-K metal gate is fabricated by employing a “dummy gate” procedure. During the fabrication process of such a semiconductor device, first, a poly-silicon is employed to occupy a gate's position (i.e. so called “dummy gate”). Then, source and drain implantations are performed, and finally, the poly-silicon gate is replaced by a metal, thereby forming a real metal gate.
FIG. 1 and FIG. 2 are diagrams showing a structure of a prior art semiconductor device. As shown in the figures, after forming, a shallow trench isolation, a gate oxide is formed on a semiconductor substrate 102 and a poly-silicon layer is deposited on the gate oxide, and then a first poly-silicon gate 103, a second poly-silicon gate 104 and a third poly-silicon gate 105 are formed directly by etching the poly-silicon layer. However, since the surface of an insulator (e.g. silicon oxide) filled in the shallow trench isolation trench is typically higher or lower than the surface of the semiconductor substrate 102 (for example, the surface of a first insulator 101 is higher than the surface of the semiconductor substrate 102 and the surface of a second insulator 107 is lower than the surface of the semiconductor substrate 102), the surface of the poly-silicon layer that is formed directly by deposition is not planar. As a result, the first poly-silicon gate 103, the second poly-silicon gate 104 and the third poly-silicon gate 105 formed in such way have different heights. Hereinto, the first poly-silicon gate 103 is higher than the surrounding second poly-silicon gate 104 because the first poly-silicon gate 103 is located on the first insulator 101; the third poly-silicon gate 105 is lower than the surrounding second poly-silicon gate 104 because the third poly-silicon gate 105 is located on the second insulator 107.
During the subsequent ILD0 (interlayer dielectric) chemical mechanical planarization processing, the CMP processing needs to be performed on high aspect ratio process (HARP) material 108 (which is usually an oxide), silicon nitride 106 (SiN) and poly-silicon on a silicon substrate at the same time. However, due to height differences among each gate, the CMP processing fails to completely remove the silicon nitride 106 that covers the top of all the poly-silicon gates, which results in residues of silicon nitride 106. In FIG. 1, the first poly-silicon gate 103 is higher than the surrounding second poly-silicon gate 104, and thus, during the CMP processing, when removing the silicon nitride from an upper surface of the first poly-silicon gate 103 to expose the upper surface of the first poly-silicon gate 103, the silicon nitride on an upper surface of the second poly-silicon gate 104 is not completely removed, and a portion thereof remains. In addition, in FIG. 2, the third poly-silicon gate 105 is lower than the surrounding second poly-silicon gate 104, and thus, during the CMP processing, when removing the silicon nitride on the upper surface of the second poly-silicon gate 104 to expose the upper surface of the second poly-silicon gate 104, the nitride silicon on an upper surface of the third poly-silicon gate 105 is not completely removed, and a portion remains.
In one example, the surface of the silicon oxide in shallow isolation trench is lower than the surface of the substrate. As a result, after ILD0 CMP, there is silicon nitride remaining between the regular linear gates.